Prerequisite Courses, if any: Analog & Digital Electronics
Course Objectives:
To make students understand
To understand fundamentals of Verilog, design hierarchy and basic Verilog examples using hierarchical modeling.
To analyze combinational logic and their applications viz. Multiplexer, Decoder, Adder
To analyze sequential logic and their applications viz. Flip-flops, Registers, Counters, Shift registers.
To understand the concepts of state machines.
To understand the FPGA architecture and design flow.
Course Outcomes:
After successful completion of the course, students will be able to:
CO1: Explain the fundamentals of Verilog HDL including design hierarchy, levels of abstraction and hierarchical modeling.
CO2: Design and implement combinational logic circuits using Verilog.
CO3: Design and implement sequential circuits using Verilog.
CO4: Design and implement Finite State Machines using Verilog.
CO5: Elaborate FPGA architecture and apply the FPGA design flow for hardware implementation.
- Teacher: Umesh Balkishan Phiske